BY ROBERT R. COLLINS
P54C Specification Clarification
For Correct Translations, the TLB Should be Flushed After
the PSE Bit in CR4 is Set.
Memory mapping tables may be changed by
setting the page size extension bit in CR4 (bit 4).
However, if the TLB is not flushed after the CR4.PSE bit
is set, it may provide an erroneous 4K-byte page
translation rather than the new 4M-byte translation, or
the other way around. Therefore, for correct
translations, the TLB should be flushed by writing to CR3
after the CR4.PSE bit is set.
This will be added to the
Pentium Processor Family Developer's Manual, Volume 3,
Sections 10.1.3 and 11.3.5.
Who says that the Intel Secrets web site doesn't make
a difference? This anomaly was first documented in my May
1996 article in Dr. Dobb's Journal entitled: Understanding 4M Page
Size Extensions on the Pentium Processor. Even though
the article appeared in the May 1996 edition, it was
published in April, 1996 -- two months before Intel's
specification update appeared.
As I mentioned in my article, I don't consider this
behavior a bug, but an anomaly instead. Intel's
documentation clearly states that it's the operating
system's responsibility to invalidate the TLB after
changes are made to paging tables, or paging structures.
Modifying CR4.PSE changes in the paging translation
mechanism. In essence, modifying CR4.PSE is analogous to
modifying the paging structures, and is therefore covered
by the caveats mentioned in Intel's documentation.
Therefore, I believe that Intel made the right decision
in documenting this behavior, instead of trying to fix
There isn't any doubt in my mind that my article
brought this anomaly to Intel's attention. Even so, this
should serve as a blatant reminder that big brother is
always watching me.